1. Field of the Invention
The present invention relates to a timing verification checking value extracting method used for the timing verification of pulses of a semiconductor integrated circuit.
2. Description of Related Art
In a design stage of a semiconductor integrated circuit, one or more input pulses are respectively input to a designed cell as a simulation, and it is checked whether or not one or more output pulses respectively reach an expected value within a prescribed time in response to the input pulses. Therefore, it is verified whether the input timing of the input pulses input to the designed cell is good or bad.
FIG. 17 is a flow chart showing a conventional timing verification checking value extracting method. As a prior art, a set up value is extracted as a timing verification checking value according to this conventional timing verification checking value extracting method of FIG. 17. For example, in case of the timing verification of pulses of a D type flip-flop circuit 11 shown in FIG. 3, the set up value denotes a time period required for the setting up of a data pulse 15 before the level change of a clock pulse 16 so as to prevent an erroneous operation of the D type flip-flop circuit 11.
As shown in FIG. 17, a waveform table and circuit connection information are prepared in advance (steps ST1 and ST2). In the waveform table, waveforms of both the data pulse 15 and the clock pulse 16 to be input to the D type flip-flop circuit 11, an initial setting value of a pulse 5 time difference 18 between the data pulse 15 and the clock pulse 16, an initial changing degree of the pulse time difference 18, a simulation completion time and a convergence condition of the pulse time difference 18 are written. Also, the circuit connection information indicates the arrangement of a plurality of transistors, resistors and capacitors composing the D type flip-flop circuit 11.
Thereafter, a group of steps 3, 4, 5 and 7 corresponding to one simulation stage is repeatedly performed. That is, a data pulse 15 and a clock pulse 16 to be input to the D type flip-flop circuit 11 are produced according to a setting value of the pulse time difference 18 and a changing degree of the pulse time difference 18 in a pulse producing process (step ST3). More precisely, in a first simulation stage of the step ST3, the data pulse 15 and the clock pulse 16 are produced so as to make the data pulse 15 earlier than the clock pulse 16 by the initial setting value written in the waveform table, and the changing degree of the pulse time difference 18 is set to the initial changing degree written in the waveform table.
Thereafter, in a simulation process (step ST4), the data pulse 15 is supplied to a data input terminal 12 of the D type flip-flop circuit 11, the clock pulse 16 is supplied to a clock input terminal 13 of the D type flip-flop circuit 11 at the pulse time difference 18 from the data pulse 15, a level of an output pulse 17 output from an output terminal 14 of the D type flip-flop circuit 11 is checked at the simulation completion time written in the waveform table, and it is judged whether the level of the output pulse 17 is good or bad.
The judgment of the level of the output pulse 17 is shown with the level changes of the pulses 15, 16 and 17 in FIG. 5. As shown in FIG. 5, a circuit simulation is started at a simulation start time 21, and it is judged whether the level of the output pulse 17 (an output pulse 17a or an output pulse 17b) becomes higher than a reference voltage 23 until the simulation completion time 22. In cases where the pulse time difference 18 is large, the level of the output pulse 17a corresponding to the large pulse time difference 18 becomes higher than the reference voltage 23 until the simulation completion time 22 in response to the inputting of a data pulse 15a corresponding to the large pulse time difference 18 and the clock pulse 16, and it is judged that the level of the output pulse 17a is good. This judgment is called an affirmative judgment in this specification. In contrast, in cases where the pulse time difference 18 is small, the level of the output pulse 17bcorresponding to the small pulse time difference 18 does not become higher than the reference voltage 23 until the simulation completion time 22 in response to the inputting of a data pulse 15b corresponding to the small pulse time difference 18 and the clock pulse 16, and it is judged that the level of the output pulse 17b is not good. This judgment is called a negative judgment in this specification. Therefore, in cases where the pulse time difference 18 between the data pulse 15 and the clock pulse 16 is large, it is judged that the input timing of the data pulse 15 satisfies the set up value which denotes a time period required for the setting up of the data pulse 15 before the level change of the clock pulse 16 so as to prevent an erroneous operation of the D type flip-flop circuit 11 (the affirmative judgment). In contrast, in cases where the pulse time difference 18 is small, it is judged that the input timing of the data pulse 15 does not satisfy the set up value (the negative judgment). In the simulation process performed in the first simulation stage, as shown in FIG. 6, because the pulse time difference 18 is set to the initial setting value 26 (indicated by a simulation stage number (1) in FIG. 6) which is sufficiently high, the affirmative judgment is obtained.
After this simulation process (step ST4) is performed, it is judged in a convergence judging process (step ST5) whether or not a changing degree of the pulse time difference 18 is within a prescribed range. As shown in FIG. 6, because a changing degree of the pulse time difference 18 is set to the initial changing degree 27 in the first simulation stage, the changing degree of the pulse time difference 18 is not within the prescribed range. Therefore, the convergence condition is not satisfied. Thereafter, in cases where it is judged in the convergence judging process that the changing degree of the pulse time difference 18 is out of the prescribed range, a pulse time difference resetting process (step ST7) is performed. In this process, a setting value of the pulse time difference 18 set in the pulse producing process (step ST3) is changed according to the judgment performed in the simulation process (step ST4), and a changing degree of the pulse time difference set in the pulse producing process (step ST3) is reduced in cases where the affirmative (or negative) judgment of the simulation process obtained in a preceding simulation stage changes to the negative (or affirmative) judgment in a current simulation stage.
More precisely, as shown in FIG. 6, in cases where the affirmative judgment of the simulation process is obtained in both the preceding and current simulation stages, the setting value of the pulse time difference 18 is decreased by the changing degree of the pulse time difference 18, and the changing degree of the pulse time difference 18 is maintained. Also, in cases where the affirmative judgment of the simulation process obtained in the preceding simulation stage changes to the negative judgment in the current simulation stage, because a set up truth value 29 to be idealistically extracted exists between a pulse time difference in the preceding simulation stage and a pulse time difference in the current simulation stage, the changing degree of the pulse time difference 18 is halved, and the setting value of the pulse time difference 18 is increased by the halved changing degree. Also, in cases where the negative judgment of the simulation process obtained in the preceding simulation stage changes to the affirmative judgment in the current simulation stage, because the set up truth value 29 exists between pulse time differences of the preceding and current simulation stages, the changing degree of the pulse time difference 18 is halved, and the setting value of the pulse time difference 18 is decreased by the halved changing degree. Also, when the affirmative judgment of the simulation process is obtained in the first simulation stage, the initial setting value of the pulse time difference 18 is decreased by theinitial changing degree of the pulse time difference 18.
Thereafter, the pulse producing process (step ST3) is again performed. In this process, a data pulse 15 and a clock pulse 16 are again produced so as to satisfy the setting value of the pulse time difference 18 and the changing degree of the pulse time difference 18 reset in the pulse time difference resetting process (step ST7). Thereafter, the simulation process (step ST4) and the convergence judging process (step ST5) are performed in the same manner as that in the preceding simulation stage. In cases where the convergence condition is not satisfied in the convergence judging process, the pulse time difference resetting process (step ST7), the pulse producing process (step ST3), the simulation process (step ST4) and the convergence judging process (step ST5) are again performed.
Therefore, because the setting value of the pulse time difference 18 and the changing degree of the pulse time difference 18 are repeatedly reset in the pulse time difference resetting process to make the setting value of the pulse time difference 18 approach the set up truth value 29, it is finally judged in the convergence judging process (step ST5) that a changing degree of the pulse time difference 18 is within the prescribed range, and the convergence condition is satisfied.
Thereafter, in a checking value extracting process (step ST8), in cases where the affirmative judgment is obtained in the simulation process of the final simulation stage, because the setting value of the pulse time difference 18 finally reset in the pulse time difference resetting process (step ST7) can be adopted as the set up value, the setting value of the pulse time difference 18 finally reset is extracted as a timing verification checking value. Also, in cases where the negative judgment is obtained in the simulation process of the final simulation stage, because the setting value of the pulse time difference 18 finally reset in the pulse time difference resetting process (step ST7) cannot be adopted as the set up value, the setting value of the pulse time difference 18 reset in the pulse time difference resetting process (step ST7) in a specific simulation stage (usually just before the final simulation stage), in which the affirmative judgment is finally obtained in the simulation process, is extracted as a timing verification checking value. Therefore, the timing verification checking value can be extracted.
However, because the conventional timing verification checking value extracting method is performed according to the processing of FIG. 17, in cases where the conventional timing verification checking value extracting method is performed for various circuits, the simulation completion time 22 depending on each circuit is not properly set. That is, in cases where the simulation completion time 22 is set to be sufficiently later than the simulation start time 21, a simulation time period required for each simulation process is lengthened. Therefore, there is a problem that it takes a lot of time to extract a timing verification checking value. In contrast, in cases where the simulation completion time 22 is set to be insufficiently later than the simulation start time 21, the negative judgment is obtained in the first simulation stage. Therefore, there is a problem that the conventional timing verification checking value extracting method cannot be performed.
An object of the present invention is to provide, with due consideration to the drawbacks of the conventional timing verification checking value extracting method, a timing verification checking value extracting method in which a timing verification checking value is reliably extracted without taking a lot of time.
The object is achieved by the provision of a timing verification checking value extracting method, comprising:
a pulse producing step for producing two input pulses having a pulse time difference of which a setting value is set to an initial setting value in advance;
a simulation step for supplying each of the input pulses produced in the pulse producing step to an input terminal of a to-be-timing-verified circuit and judging, until a simulation completion time set in advance, whether or not an output pulse output from an output terminal of the to-be-timing-verified circuit is good;
an optimum simulation completion time determining step for determining an optimum simulation completion time, which is to be used in the simulation step as the simulation completion time in simulation stages following a first simulation stage, according to a level change time at which the output pulse is changed to a stable level in the first simulation stage;
a pulse time difference resetting step for resetting the setting value of the pulse time difference between the input pulses, which is to be produced in the pulse producing step in a succeeding simulation stage following a current simulation stage, according to the judgment of the simulation step of the current simulation stage by changing the setting value of the pulse time difference by a changing degree, and reducing the changing degree of the pulse time difference in cases where the judgment of the simulation step in the current stage differs from that in a simulation stage preceding to the current stage;
a convergence judging step for judging whether or not the changing degree of the pulse time difference reset in the pulse time difference resetting step is within a prescribed range and making the pulse producing step, the simulation step, the optimum simulation completion time determining step and the pulse time difference resetting step be repeatedly performed until the changing degree of the pulse time difference becomes within the prescribed range; and
a checking value extracting step for extracting the pulse time difference between the input pulses as a timing verification checking value according to the judgment performed in the convergence judging step.
In the above steps, though the judgment whether or not the output pulse is good is performed until the simulation completion time set in advance in the simulation step of the first simulation stage, the judgment is performed until an optimum simulation completion time, which is determined in the optimum simulation completion time determining step, in the simulation step of each simulation stage following the first simulation stage. Therefore, a simulation time required in the simulation step, in which the judgment is performed until the optimum simulation completion time, is shortened as compared with that required in the simulation step in which the judgment is performed until the simulation completion time set in advance.
Accordingly, the timing verification checking value can be reliably extracted at high speed.
The object is also achieved by the provision of a timing verification checking value extracting method, comprising:
a pulse producing step for producing two input pulses having a pulse time difference, of which a setting value is set to an initial setting value in advance, and respectively having a pulse inclination;
a simulation step for supplying each of the input pulses produced in the pulse producing step to an input terminal of a to-be-timing-verified circuit and judging whether or not an output pulse output from an output terminal of the to-be-timing-verified circuit is good;
a pulse time difference resetting step for resetting the setting value of the pulse time difference between the input pulses, which is to be produced in the pulse producing step in a succeeding simulation stage following a current simulation stage, according to the judgment of the simulation step of the current simulation stage by changing the setting value of the pulse time difference by a changing degree, and reducing the changing degree of the pulse time difference in cases where the judgment of the simulation step in the current stage differs from that in a simulation stage preceding to the current stage;
a convergence judging step for judging whether or not the changing degree of the pulse time difference reset in the pulse time difference resetting step is within a prescribed range and making the pulse producing step, the simulation step and the pulse time difference resetting step be repeatedly performed until the changing degree of the pulse time difference becomes within the prescribed range;
a checking value extracting step for extracting the pulse time difference between the input pulses respectively having the pulse inclination as a timing verification checking value according to the judgment performed in the convergence judging step;
a pulse inclination resetting step for setting the pulse inclinations of the input pulses, which are produced in the pulse producing step, to a set of first pulse inclinations to extract the pulse time difference between the input pulses having the first pulse inclinations as a timing verification checking value in the checking value extracting step, resetting the pulse inclinations of the input pulses, which are produced in the pulse producing step, to a set of second pulse inclinations to extract the pulse time difference between the input pulses having the second pulse inclinations as a timing verification checking value in the checking value extracting step, and resetting the pulse inclinations of the input pulses, which are produced in the pulse producing step, to a set of third pulse inclinations between the set of first pulse inclinations and the set of second pulse inclinations to extract the pulse time difference between the input pulses having the third pulse inclinations as a timing verification checking value in the checking value extracting step; and
an initial pulse time difference setting step for setting the pulse time difference for the input pulses, which are produced in the pulse producing step and have the third pulse inclinations reset in the pulse inclination resetting step, to a particular setting value according to the timing verification checking value, which is extracted in the checking value extracting step and corresponds to the input pulses having the first pulse inclinations, and the timing verification checking value, which is extracted in the checking value extracting step and corresponds to the input pulses having the second pulse inclinations, to produce the input pulses having the pulse time difference set to the particular setting value and having the third pulse inclinations in the pulse producing step.
In the above steps, after the pulse time difference between the input pulses having the first pulse inclinations and the pulse time difference between the input pulses having the second pulse inclinations are extracted in the checking value extracting step, the pulse inclinations of the input pulses are reset in the pulse inclination resetting step to a set of third pulse inclinations between the set of first pulse inclinations and the set of second pulse inclinations, and the initial setting value of the pulse time difference for the input pulses having the third pulse inclinations is set to the particular setting value in the initial pulse time difference setting step according to the timing verification checking value of the input pulses having the first pulse inclinations and the timing verification checking value of the input pulses having the second pulse inclinations. For example, the pulse time difference for the input pulses having the third pulse inclinations is set to an average value between the timing verification checking values. Thereafter, the input pulses having the pulse time difference set to the particular setting value and having the third pulse inclinations are produced in the pulse producing step.
Accordingly, because the pulse time difference for the input pulses having the third pulse inclinations is not set to the initial setting value but is set to the particular setting value near to a timing verification checking value to be idealistically extracted, the timing verification checking value for the input pulses having the third pulse inclinations can be reliably extracted at high speed.
It is preferred that the timing verification checking value extracting method further comprises
a pulse time difference initial changing degree setting step for setting the changing degree of the pulse time difference to a particular changing degree according to the particular setting value of the pulse time difference set in the initial pulse time difference setting step and either the timing verification checking value, which is extracted in the checking value extracting step and corresponds to the input pulses having the first pulse inclinations, or the timing verification checking value, which is extracted in the checking value extracting step and corresponds to the input pulses having the second pulse inclinations, to reset the setting value of the pulse time difference for the input pulses having the third pulse inclinations according to the particular changing degree of the pulse time difference in the pulse time difference resetting step.
In the above step, the changing degree of the pulse time difference for the input pulses having the third pulse inclinations is set to a particular changing degree in the pulse time difference initial changing degree setting step, and the setting value of the pulse time difference for the input pulses having the third pulse inclinations is reset in the pulse time difference resetting step by changing the setting value of the pulse time difference by the particular changing degree.
Accordingly, because the setting value of the pulse time difference for the input pulses having the third pulse inclinations is not changed by a changing degree set in advance but is changed by the particular changing degree, an extraction time required to extract the timing verification checking value corresponding to the input pulses having the third pulse inclinations in the checking value extracting step can be shortened.
It is also achieved by the provision of a timing verification checking value extracting method, comprising:
a pulse producing step for producing two input pulses having a pulse time difference of which a setting value is set to an initial setting value in advance;
a simulation step for supplying each of the input pulses produced in the pulse producing step to an input terminal of a to-be-timing-verified circuit and judging whether or not an output pulse output from an output terminal of the to-be-timing-verified circuit is good;
a pulse time difference resetting step for repeatedly performing the resetting of the setting value of the pulse time difference between the input pulses, which is to be produced in the pulse producing step in a succeeding simulation stage following a current simulation stage, according to the judgment of the simulation step of the current simulation stage by changing the setting value of the pulse time difference by a changing degree until the judgment of the simulation step of the current simulation stage differs from that of a simulation stage preceding to the current simulation stage to place the pulse time difference in the neighborhood of a set up truth value, repeatedly performing the resetting of the setting value of the pulse time difference between the input pulses, which is to be produced in the pulse producing step in the succeeding simulation stage, according to the judgment of the simulation step of the current simulation stage by changing the setting value of the pulse time difference by the changing degree until the judgment of the simulation step of the current simulation stage again differs from that of a simulation stage preceding to the current simulation stage to place the pulse time difference in the neighborhood of a hold truth value, repeatedly performing the resetting of the setting value of the pulse time difference placed in the neighborhood of the set up truth value while reducing the changing degree of the pulse time difference according to the judgment of the simulation step of the current simulation stage and repeatedly performing the resetting of the setting value of the pulse time difference placed in the neighborhood of the hold truth value while reducing the changing degree of the pulse time difference according to the judgment of the simulation step of the current simulation stage;
a convergence judging step for judging whether or not the changing degree of the pulse time difference reset in the pulse time difference resetting step is within a prescribed range, making the pulse producing step, the simulation step and the pulse time difference resetting step be repeatedly performed until the changing degree of the pulse time difference placed in the neighborhood of the set up truth value becomes within the prescribed range and again making the pulse producing step, the simulation step and the pulse time difference resetting step be repeatedly performed until the changing degree of the pulse time difference placed in the neighborhood of the hold truth value becomes within the prescribed range; and
a checking value extracting step for extracting the pulse time difference between the input pulses as a timing verification checking value denoting a set up value, in cases where it is judged in the convergence judging step that the changing degree of the pulse time difference placed in the neighborhood of the set up truth value is within the prescribed range, and extracting the pulse time difference between the input pulses as a timing verification checking value denoting a hold value in cases where it is judged in the convergence judging step that the changing degree of the pulse time difference placed in the neighborhood of the hold truth value is within the prescribed range.
In the above steps, the pulse time difference is changed by the changing degree every simulation stage in the pulse time difference resetting step until the judgment of the simulation step of the current simulation stage differs from that of a simulation stage preceding to the current simulation stage, so that the pulse time difference is placed in the neighborhood of a set up truth value to be idealistically extracted as a timing verification checking value. Thereafter, the pulse time difference is again changed by the changing degree every simulation stage in the pulse time difference resetting step until the judgment of the simulation step of the current simulation stage differs from that of the preceding simulation stage, so that the pulse time difference is placed in the neighborhood of a hold truth value to be idealistically extracted as a timing verification checking value.
Thereafter, the pulse time difference placed in the neighborhood of the set up truth value is changed by the changing degree every simulation stage in the pulse time difference resetting step while reducing the changing degree of the pulse time difference according to the judgment of the simulation step of the current simulation stage. In cases where it is judged in the convergence judging step that the changing degree of the pulse time difference is within the prescribed range, the pulse time difference between the input pulses is extracted as a timing verification checking value denoting a set up value in the checking value extracting step.
Thereafter, the pulse time difference placed in the neighborhood of the hold truth value is changed by the changing degree every simulation stage in the pulse time difference resetting step while reducing the changing degree of the pulse time difference according to the judgment of the simulation step of the current simulation stage. In cases where it is judged in the convergence judging step that the changing degree of the pulse time difference is within the prescribed range, the pulse time difference between the input pulses is extracted as a timing verification checking value denoting a hold value in the checking value extracting step.
Accordingly, because the simulation, which is repeatedly performed in the simulation step for the input pulses having the pulse time difference to place the pulse time difference in the neighborhood of the set up truth value, is common to both the extraction of the timing verification checking value denoting a set up value and the extraction of the timing verification checking value denoting a hold value, the timing verification checking values can be rapidly extracted.
It is applicable that the simulation step comprising the steps of:
detecting a delay time which extends from the supply of the one input pulse to the to-be-timing-verified circuit to the production of the output pulse and changes with the pulse time difference; and
judging that the output pulse is not good in cases where the delay time is longer than a prescribed limit.
In the above steps, in cases where the delay time is longer than a prescribed limit, there is a possibility that the to-be-timing-verified circuit such as a D type flip-flop circuit is erroneously operated. Therefore, in cases where the delay time is longer than a prescribed limit, it is judged that the output pulse is not good.
Accordingly, the timing verification checking value can be reliably extracted with high precision without erroneously operating the to-be-timing-verified circuit.
It is applicable that the simulation step comprising the steps of:
detecting a pulse inclination of one input pulse changing with the pulse time difference; and
judging that the output pulse is not good in cases where the pulse inclination exceeds a prescribed limit.
In the above steps, in cases where the pulse inclination exceeds a prescribed limit, there is a possibility that the to-be-timing-verified circuit such as a D type flip-flop circuit is erroneously operated. Therefore, in cases where the pulse inclination exceeds a prescribed limit, it is judged that the output pulse is not good.
Accordingly, the timing verification checking value can be reliably extracted with high precision without erroneously operating the to-be-timing-verified circuit.
It is preferred that one of the input pulses produced in the pulse producing step has a pulse width of which a setting value is set to an initial setting value in advance, the setting value of the pulse width of the input pulse is reset in the pulse time difference resetting step according to the judgment of the simulation step of the current simulation stage by changing the setting value of the pulse width by a changing degree, the changing degree of the pulse width is reduced in the pulse time difference resetting step in cases where the judgment of the simulation step in the current stage differs from that in a simulation stage preceding to the current stage, it is judged in the convergence judging step whether or not the changing degree of the pulse width reset in the pulse time difference resetting step is within a prescribed range, and the pulse width is extracted in the checking value extracting step as a timing verification checking value in cases where it is judged in the convergence judging step that the pulse width is within the prescribed range.
In the above steps, the pulse width of one input pulse is extracted in place of the pulse time difference between the input pulses as a timing verification checking value.
Accordingly, the pulse width can be reliably extracted as a timing verification checking value.
It is preferred that the checking value extracting step comprises the steps of:
extracting the pulse time difference finally reset in the pulse time difference resetting step as a timing verification checking value in cases where it is judged in the simulation step of the final simulation stage that the output pulse is good; and
extracting the pulse time difference corresponding to a specific simulation stage, in which it is finally judged that the output pulse is good, in cases where it is judged in the simulation step of the final simulation stage that the output pulse is not good.
In the above steps, because the pulse time difference extracted as a timing verification checking value always corresponds to the final judgment that the output pulse is good, the timing verification checking value can be reliably extracted.